In a low power All Digital Phase Locked Loop (ADPLL) such as described, for example, in Chillara et al., “An 860 μW 2.1-to-2.7 GHz All-Digital PLL-Based Frequency Modulator with a DTC-Assisted Snapshot TDC for WPAN (Bluetooth Smart and ZigBee) Applications,” IEEE INTI SOLID-STATE CIRCUITS CONFERENCE (ISSCC) (2014), the clock edges of a digitally controlled oscillator (DCO) are retimed via a Digital-to-Time Converter (DTC) such that a power-hungry Time-to-Digital Converter (TDC) can be reduced in size. During initial locking, an asynchronous counter is used as a phase incrementor to calibrate the DCO. The counter is a power-hungry block that is switched off as soon as possible. For final phase locking, the tracking bank is used, and the counter is switched off. This set-up has, however, the disadvantage that the ADPLL can be easily pulled to a false locking state by a frequency disturbance when the counter is switched off, such that the counter needs to be switched back on, thereby increasing energy consumption of the ADPLL. In this false locking state, the TDC output is continuously switching between maximum and minimum output values, creating a stable point at an undesired frequency.